1. Field of the Invention
The present invention relates to a non-volatile memory having a FLOTOX (Floating Gate Oxide) type field effect transistor provided with a floating gate on a semiconductor substrate through a tunnel oxide film; and a method for manufacturing the same, and more particularly to the improvement of a tunnel window for injecting charges to the floating gate through the tunnel oxide film so as to perform data programming.
2. Description of the Prior Art
Conventionally, there has been known a non-volatile memory for injecting charges to a floating gate through a tunnel oxide film and accumulating the same therein, and for changing the threshold of a FLOTOX type FET (field effect transistor) so as to store information, which is shown in FIG. 16.
As shown in FIG. 16, a non-volatile memory mainly comprises a FLOTOX type FET 40 provided with a SiO.sub.2 tunnel oxide film 24a, and a FET 41 for selecting the FLOTOX type FET 40 on a P-type Si substrate 21 provided with the N.sup.+ diffused layer 30 of a source-drain having As ions.
The FLOTOX type FET 40 includes a polysilicon floating gate 28 provided on the Si substrate 21 through the tunnel oxide film 24a, and a polysilicon control gate 32 provided on the floating gate 28 through a SiO.sub.2 thermal oxide film 31 so as to cover the floating gate 28.
The FET 41 includes a selective gate 27 and a SiO.sub.2 gate oxide film 22c on the Si substrate 21 on which the FLOTOX type FET 40 is formed. The selective gate 27 is provided through the SiO.sub.2 gate oxide film 22c having a greater thickness than that of the tunnel oxide film 24a. The SiO.sub.2 thermal oxide film 31 covers the selective gate 27.
A window 50 for writing and erasing is formed on a floating gate end on the FET 41 side in the tunnel oxide film 24a.
There will be described a manufacturing method.
At first, a SiO.sub.2 oxide film 22 is formed at a thickness of 300 .ANG. over a P-type Si substrate 21 by a known thermal oxidation method so as to function as the gate oxide film 22c of a FET 41 [see FIGS. 10 and 16].
Then, a resist pattern 20 is formed on the SiO.sub.2 oxide film 22 by a photoetching technology. The SiO.sub.2 oxide film 22 in a region 23 which at least includes a floating gate formation region, is removed by using the resist pattern 20 as a mask [see FIG. 11].
In that case, a SiO.sub.2 film 22b remains in a region S in which the FET 41 is formed. In addition, a SiO.sub.2 film 22a is caused to remain in a region T opposed to the SiO.sub.2 film 22b with the region 23 interposed therebetween. Then, the resist pattern 20 is removed.
Thereafter, a tunnel oxide film (SiO.sub.2 film) 24 is formed at a thickness of 80 .ANG. in the region 23 by the known thermal oxidation method [see FIG. 12].
A polysilicon layer 25 having a thickness of 2000 .ANG. is laminated on the SiO.sub.2 films 22a, 22b and 24. Resist patterns 26a and 26b for forming a floating gate and a selective gate are formed on the polysilicon layer 25 [see FIG. 13].
As shown in FIG. 14, the polysilicon layer 25 is removed with the use of the resist patterns 26a and 26b as masks by the photoetching technology so as to form a floating gate 28 add a selective gate 27. Then, As ions 29 are implanted so as to form N.sup.+ diffused layers 30 by high temperature annealing for 30 minutes at a temperature of 900.degree. C. [see FIG. 14].
In that case, a tunnel window 50 is formed on a self-aligning basis on the tunnel oxide film 24 on the selective gate 27 side just below a floating gate 28 end.
Subsequently, the SiO.sub.2 films 24, 22a and 22b are removed by using the selective gate 27 and floating gate 28 as masks [see FIG. 15]. The SiO.sub.2 films 22c and 24a remaining just below the selective gate 27 and floating gate 28 are their gate oxide film 22c and tunnel oxide film 24a, respectively. As described above, the tunnel oxide film 24a has the window 50 provided just below the floating gate 28 end on the selective gate 27 side.
Finally, the Si substrate 21 including the gates 27 and 28 is subjected to thermal oxidation so as to form a SiO.sub.2 film 31 having a thickness of 200 .ANG. as a gate oxide film for a control gate. More specifically, the SiO.sub.2 thermal oxide film 31 is formed so as to cover the N.sup.+ diffused layers 30, the selective gate 27 and the floating gate 28. Then, a polysilicon layer is laminated at a thickness of 2000 .ANG. over the thermal oxide film 31. Thereafter, a control gate 32 is formed by patterning on the floating gate 28 through the thermal oxide film 31. Thus, a memory is manufactured [see FIG. 16].
The thermal oxide film 31 as the gate oxide film for the control gate 32 is formed by the thermal oxidation method. Referring to the prior art, the Si substrate 21 including the gates 27 and 28 is subjected to thermal oxidation with the SiO.sub.2 film 22c and the SiO.sub.2 film 24a having the tunnel window 50, which have different thicknesses, included therein as shown in FIG. 15. Consequently, a floating gate end 28a on the selective gate 27 side is raised upward [see FIG. 16]. As a result, the thickness of the tunnel oxide film 24a having the window for writing and erasing becomes greater than before thermal oxidation. In the tunnel window 50, the above-mentioned tendency is particularly marked, so that writing and erasing characteristics may be deteriorated.
It is an object of the present invention to provide a non-volatile memory capable of preventing a floating gate end from being raised when forming a gate oxide film for a floating gate by thermal oxidation, and a method for manufacturing the same.